1. Field of the Invention
The present invention relates to a programmable controller, particularly to a programmable controller including an instruction cache for rapidly processing a branch instruction.
2. Description of the Related Art
A procedure of executing a branch instruction such as CALL or JUMP in a programmable controller for executing a sequence program is as follows.
<1> Address data of an external memory is set in a program counter (PC) for a sequence program inside a processor.
<2> The processor outputs the address data to the external memory.
<3> The external memory outputs program code data.
<4> The processor takes and executes the program code data.
When the sequence program is stored in the external memory to the programmable controller, there is a time-lag between when the program counter (PC) is set and when the program starts to be executed, as illustrated in FIG. 5. The time-lag causes a longer branch instruction processing time. In order to avoid the problem that the branch instruction processing time is longer, for example, as disclosed in Japanese Patent Application Laid-Open No. 2001-22577 Publication or Patent Application No. 2010-509680 Publication, an instruction cache for storing a branch destination program code therein is generally provided, and the program code is rapidly read from the cache when a branch occurs, thereby shortening the processing time when the branch occurs (see FIG. 6 and FIG. 7).
As described above, also in a structure using the instruction cache, there is a problem that when the number of branch destinations is larger than the number of entries in the instruction caches, before the processor refers to the instruction cache, the instruction cache is always overwritten and no cache hit is found, and the instruction cache does not always operate validly.